6.17 System Interface Request and Response Protocol
Processor Request Protocol
A processor request is generated when the R10000 processor requires a system resource.
The processor may only issue a processor request when the System interface is in master state. If the System interface is in master state, the processor may issue a processor request immediately. Processor requests may occur in adjacent SysClk cycles. If the System interface is not in master state, the processor must first assert SysReq*, and then wait for the external agent to relinquish mastership of the System interface bus by asserting SysGnt* and SysRel*.
When multiple, nonconflicting processor requests and/or coherency data responses are ready and meet all issue requirements, the processor uses the following priority:
- block read and upgrade requests have the highest priority, followed by
- processor coherency data responses,
- processor eliminate and typical block write requests,
- processor double/single/partial-word read/write and uncached accelerated block write requests, which have the lowest priority.
Processor Block Read Request Protocol
A processor block read request results from a cached instruction fetch, load, store, or prefetch that misses in the secondary cache. Before issuing a processor block read request, the processor changes the secondary cache state to Invalid. Additionally, if the secondary cache block former state was DirtyExclusive, a write back is scheduled. Note that if the processor block read request receives an external NACK or ERR completion response, the secondary cache block state remains Invalid. (See page 102 in Errata.)
The processor issues a processor block read request with a single address cycle. The address cycle consists of the following:
The processor may only issue a processor block read request address cycle when the following are true:
A single processor may have as many as four processor block read requests outstanding on the System interface at any given time.
Figure 6-10 depicts four processor block read requests. Since the System interface is initially in slave state, the processor must first assert SysReq* and then wait until the external agent relinquishes mastership of the System interface by asserting SysGnt* and SysRel*.
Figure 6-10 Processor Block Read Request Protocol
A processor double/single/partial-word read request results from an uncached instruction fetch or load.
The processor issues a processor double/single/partial-word read request with a single address cycle. The address cycle consists of:
The processor may only issue a processor double/single/partial-word read request address cycle when:
A single processor may have a maximum of one processor double/single/partial-word read request outstanding on the System interface at any given time.
Figure 6-11 depicts a processor double/single/partial-word read request. Since the System interface is initially in slave state, the processor must first assert SysReq* and then wait until the external agent gives up mastership of the System interface by asserting SysGnt* and SysRel*.
Figure 6-11 Processor Double/Single/Partial-Word Read Request Protocol
A processor block write request results from the following:
- replacement of a DirtyExclusive secondary cache block due to a load, store, or prefetch secondary cache miss
- a CACHE Index WriteBack Invalidate (S) or Hit WriteBack Invalidate (S) instruction
- a completely gathered uncached accelerated block
As shown in Figure 6-12, the processor issues a processor block write request with a single address cycle followed by 8 or 16 data cycles.
The address cycle consists of the following:
- negating SysCmd[11]
- driving the block write command on SysCmd[7:5]
- driving the write cause indication on SysCmd[4:3]
- driving the target indication on SysAD[63:60]
- driving the physical address on SysAD[39:0]
- asserting SysVal*
If the processor block write request results from the writeback of a secondary cache block, the Dirty Exclusive secondary cache block former state is driven on SysAD[2:1], the secondary cache block way is driven on SysAD[57] and SysCmd[0] is asserted. (See page 106 in Errata)
If the processor block write request results from a completely gathered uncached accelerated block, the uncached attribute is driven on SysAD[59:58] and SysCmd[0] is negated. (See page 106 in Errata)
Each data cycle consists of the following:
- asserting SysCmd[11]
- driving the data quality indication on SysCmd[5]
- driving the data type indication on SysCmd[4:3]
- driving the data on SysAD[63:0]
- asserting SysVal*
The first 7 or 15 data cycles have a request data type indication, and the last data cycle has a request last data type indication.
The processor may negate SysVal* between data cycles of a processor block write request only if the SCClk frequency is less than half of the SysClk frequency.
The processor may only issue a processor block write request address cycle when the following are true:
Figure 6-12 depicts two adjacent processor block write requests. Since the System interface is initially in slave state, the processor must first assert SysReq* and then wait until the external agent relinquishes mastership of the System interface by asserting SysGnt* and SysRel*.
Figure 6-12 Processor Block Write Request Protocol
A processor double/single/partial-word write request results from an uncached store or incompletely gathered uncached accelerated block.
As shown in Figure 6-13, the processor issues a processor double/single/partial-word write request with a single address cycle immediately followed by a single data cycle.
The address cycle consists of the following:
- negating SysCmd[11]
- driving the double/single/partial-word write command on SysCmd[7:5]
- driving the write cause indication on SysCmd[4:3]
- driving the data size indication on SysCmd[2:0]
- driving the target indication on SysAD[63:60]
- driving the uncached attribute on SysAD[59:58]
- driving the physical address on SysAD[39:0]
- asserting SysVal*
The data cycle consists of the following:
- asserting SysCmd[11]
- driving the request last data type indication on SysCmd[4:3]
- driving the write data on SysAD[63:0]
- asserting SysVal*
The processor may only issue a processor double/single/partial-word write request address cycle when the System interface is in master state and SysWrRdy* was asserted two SysClk cycles previously.
Figure 6-13 depicts three processor double/single/partial write requests. Since the System interface is initially in slave state, the processor must first assert SysReq* and then wait until the external agent relinquishes mastership of the System interface by asserting SysGnt* and SysRel*.
Figure 6-13 Processor Double/Single/Partial-Word Write Request Protocol
A processor upgrade request results from a store or prefetch exclusive that hits a Shared block in the secondary cache.
As shown in Figure 6-14, the processor issues a processor upgrade request with a single address cycle. This address cycle consists of the following:
- negating SysCmd[11]
- driving a free request number on SysCmd[10:8]
- driving the upgrade command on SysCmd[7:5]
- driving the upgrade cause indication on SysCmd[4:3]
- driving the secondary cache block former state on SysCmd[2:1]
- asserting SysCmd[0]
- driving the target indication on SysAD[63:60]
- driving the secondary cache block way on SysAD[57]
- driving the physical address on SysAD[39:0]
- asserting SysVal*
The processor may only issue a processor upgrade request address cycle when the following are true:
A single processor may have as many as four processor upgrade requests outstanding on the System interface at any given time.
Figure 6-14 depicts four processor upgrade requests. Since the System interface is initially in slave state, the processor must first assert SysReq* and then wait until the external agent relinquishes mastership of the System interface by asserting SysGnt* and SysRel*.
Figure 6-14 Processor Upgrade Request Protocol
A processor eliminate request results from the following:
- a cached instruction fetch, load, store, or prefetch that misses in the secondary cache and forces the replacement of a Shared or CleanExclusive secondary cache block
- a CACHE Index WriteBack Invalidate (S), Hit Invalidate (S), or Hit WriteBack Invalidate (S) instruction that forces the invalidation of a Shared or CleanExclusive secondary cache block
- a CACHE Hit Invalidate (S) instruction that forces the invalidation of a DirtyExclusive secondary cache block.
A processor eliminate request notifies the external agent that a Shared, CleanExclusive, or DirtyExclusive block has been eliminated from the secondary cache. Such requests are useful for systems implementing a directory-based coherency protocol, and are enabled by asserting the PrcElmReq mode bit.
The processor issues a processor eliminate request with a single address cycle. This address cycle consists of the following:
The processor may only issue a processor eliminate request address cycle when the following are true:
Figure 6-15 depicts three processor eliminate requests. Since the System interface is initially in slave state, the processor must first assert SysReq* and then wait until the external agent relinquishes mastership of the System interface by asserting SysGnt* and SysRel*.
Figure 6-15 Processor Eliminate Request Protocol
The processor provides the signals SysRdRdy* and SysWrRdy* to allow an external agent to control the flow of processor requests. SysRdRdy* controls the flow of processor read and upgrade requests whereas SysWrRdy* controls the flow of processor write and eliminate requests.
The processor can only issue a processor read or upgrade request address cycle to the System interface if SysRdRdy* was asserted two SysClk cycles previously. Similarly, the processor can only issue the address cycle of a processor write or eliminate request to the System interface if SysWrRdy* was asserted two SysClk cycles previously.
To determine the processor request buffering requirements for the external agent, note that the processor can issue any combination of processor requests in adjacent SysClk cycles. Also, since the System interface operates register-to-register with the external agent, a round trip delay of four SysClk cycles occurs between a processor request address cycle which prompts the external agent for flow control, and the flow control actually preventing any additional processor request address cycles from occurring. Consequently, if the maximum number of outstanding processor requests specified by the PrcReqMax mode bits is four, the external agent must be able to accept at least four processor read or upgrade requests. Also, the external agent must be able to accept at least four processor eliminate requests, two processor double/single/partial-word write requests, or one processor block write request.
Figure 6-16 depicts three processor double/single/partial-word write requests and four processor block read requests. After sensing the first processor double/single/partial-word write request, the external agent negates SysWrRdy*. The external agent must have buffering sufficient for one additional processor write request before the flow control takes effect.
The external agent negates SysRdRdy* upon observing the first processor read request. The external agent must have buffering sufficient for three additional processor read requests before the flow control takes effect.
Figure 6-16 Processor Request Flow Control Protocol
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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